You are most welcome!
This is the second of a series of five seminars bringing together FPGA practitioners, computer science and engineering experts, scientific computing experts, application owners and HPC providers. We will attempt to build a community through which we discuss and evaluate the need and usability of FPGAs in HPC and Scientific Computing. Curious about the first FIRE seminar? Check the blog of SURF.
The series is part of the FIRE symposia and is jointly organised by QBayLogic, SURF and the Hardware Accelleration Network NL.
Program
10:00-10:05 – Opening
10:05-10:30 – Design rules and automation for FPGA development at Technolution
Speakers: Edwin Hakkennes, Technical Architect and Tom van Leeuwen, Designer at Technolution
10:35-11:00 – SOCs/FPGAs: Beyond programmable functionality
Speaker: Dirk van den Heuvel, Principal Consultant at TOPIC embedded systems
11:00-11:30 – Coffee break
11:30-11:55 – Realtime FPGA processing for measurement and control applications
Speaker: Ronald Grootelaar, Consulting Engineer at Kendrion
12:00-12:25 – Efinix Titanium series of FPGAs
Speaker: not yet known, will follow later
12:30-14:00 – Lunch
14:00-14:25 – Complex Timing Constraints
Speaker: Frank de Bont, Consultant at Core|Vision
14:30-14:55 – Lattice Nexus family of FPGAs
Speaker: Etienne Janssen, Regional Sales Manager at Lattice Semiconductor
15:00-15:30 – Coffee break
15:30-15:55 – Hardware verification with Clash HDL and automated counter-example shrinking
Speaker: Martijn Bastiaan, Compiler Engineer at QBayLogic
16:00-16:25 – Using the AMD Dynamic Function eXchange (DFX) flow to achieve timing closure
Speaker: Gert-Jan Lahpor, Senior FPGA designer at Aimvalley
16:30-17:30 – drinks
Sign up
You can sign up here, until the event sells out!
Location
The event will take place at the SURF office in Utrecht, Moreelsepark 48, 3511 EP Utrecht.