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X-WR-CALNAME:The NCC Netherlands
X-ORIGINAL-URL:https://eurocc-netherlands.nl
X-WR-CALDESC:Events for The NCC Netherlands
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DTSTART:20220101T000000
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DTSTART;TZID=UTC:20231101T093000
DTEND;TZID=UTC:20231101T173000
DTSTAMP:20260403T215006
CREATED:20230908T125251Z
LAST-MODIFIED:20230914T144140Z
UID:631-1698831000-1698859800@eurocc-netherlands.nl
SUMMARY:FIRE: Industrial Users FPGAs seminar
DESCRIPTION:This “Industrial users of FPGAs” seminar aims to bring together professionals working and applying FPGAs in the Netherlands. It is a knowledge-sharing event created for and by the FPGA engineer. FIRE is short for: \nFPGA Innovation Research Exchange. \n  \n\n\n\n\nYou are most welcome!\nThis is the second of a series of five seminars bringing together FPGA practitioners\, computer science and engineering experts\, scientific computing experts\, application owners and HPC providers. We will attempt to build a community through which we discuss and evaluate the need and usability of FPGAs in HPC and Scientific Computing. Curious about the first FIRE seminar? Check the blog of SURF. \nThe series is part of the FIRE symposia and is jointly organised by QBayLogic\, SURF and the Hardware Accelleration Network NL. \nProgram\n10:00-10:05 – Opening \n10:05-10:30 – Design rules and automation for FPGA development at Technolution\nSpeakers: Edwin Hakkennes\, Technical Architect and Tom van Leeuwen\, Designer at Technolution \n10:35-11:00 – SOCs/FPGAs: Beyond programmable functionality\nSpeaker: Dirk van den Heuvel\, Principal Consultant at TOPIC embedded systems \n11:00-11:30 – Coffee break \n11:30-11:55 – Realtime FPGA processing for measurement and control applications\nSpeaker: Ronald Grootelaar\, Consulting Engineer at Kendrion \n12:00-12:25 – Efinix Titanium series of FPGAs\nSpeaker: not yet known\, will follow later \n12:30-14:00 – Lunch \n14:00-14:25 – Complex Timing Constraints\nSpeaker: Frank de Bont\, Consultant at Core|Vision \n14:30-14:55 – Lattice Nexus family of FPGAs\nSpeaker: Etienne Janssen\, Regional Sales Manager at Lattice Semiconductor \n15:00-15:30 – Coffee break \n15:30-15:55 – Hardware verification with Clash HDL and automated counter-example shrinking\nSpeaker: Martijn Bastiaan\, Compiler Engineer at QBayLogic \n16:00-16:25 – Using the AMD Dynamic Function eXchange (DFX) flow to achieve timing closure\nSpeaker: Gert-Jan Lahpor\, Senior FPGA designer at Aimvalley \n16:30-17:30 – drinks \nSign up\nYou can sign up here\, until the event sells out! \nLocation\nThe event will take place at the SURF office in Utrecht\, Moreelsepark 48\, 3511 EP Utrecht.
URL:https://eurocc-netherlands.nl/calendar/fire-industrial-users-fpgas-seminar/
LOCATION:SURF Utrecht\, Moreelsepark 48\, Utrecht\, 3511 EP\, Netherlands
CATEGORIES:Training
ATTACH;FMTTYPE=image/png:https://eurocc-netherlands.nl/wp-content/uploads/2023/09/FIRE-Industrial-users.png
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